<h1>PCB Routing Rules and Best Practices</h1> <h2>Overview</h2> <p>Proper PCB routing ensures signal integrity, manufacturability, and reliable operation. This guide covers essential routing rules.</p> <h2>Fundamental Routing Rules</h2> <h3>1. Trace Width Rules</h3> <p><strong>Current-Carrying Capacity:</strong></p> <ul> <li>Signal traces: 6-10 mil (0.15-0.25mm)</li> <li>Power traces: Calculate based on current</li> <li>General formula: 1A per 10-20 mil width for outer layers</li> </ul> <p><strong>Impedance-Controlled Traces:</strong></p> <ul> <li>Use calculator or field solver</li> <li>Depends on dielectric and stack-up</li> <li>Typical single-ended: 50-75Ω</li> <li>Differential pairs: 90-100Ω</li> </ul> <h3>2. Trace Spacing Rules</h3> <p><strong>The 3W Rule:</strong></p> <ul> <li>Distance between traces ≥ 3× trace width</li> <li>Critical for high-speed signals</li> <li>Prevents crosstalk</li> </ul> <p><strong>Clearance Requirements:</strong></p> <ul> <li>Low voltage: 6-8 mil minimum</li> <li>High voltage: Calculate based on IPC-2221</li> <li>Manufacturing limits: Follow fabricator capabilities</li> </ul> <h3>3. Via Rules</h3> <p><strong>Via Sizing:</strong></p> <ul> <li>Drill diameter: 0.2-0.3mm standard</li> <li>Pad diameter: 0.4-0.6mm</li> <li>Aspect ratio &lt; 10:1 for reliable plating</li> </ul> <p><strong>Via Placement:</strong></p> <ul> <li>Minimize via count in signal paths</li> <li>Use vias in pads for fine-pitch BGAs</li> <li>Avoid vias under components unless filled</li> </ul> <h3>4. Differential Pair Routing</h3> <p><strong>Requirements:</strong></p> <ul> <li>Match lengths within 5-10 mil</li> <li>Maintain constant spacing</li> <li>No vias between pair members</li> <li>Symmetrical routing around obstacles</li> </ul> <h3>5. High-Speed Routing Rules</h3> <p><strong>Critical Practices:</strong></p> <ol> <li>Reference planes must be continuous</li> <li>Avoid 90° bends (use 45° or curves)</li> <li>Minimize layer transitions</li> <li>Don&#39;t route over plane splits</li> <li>Keep traces as short as possible</li> </ol> <h2>Design Rule Check (DRC)</h2> <p><strong>Essential DRC Settings:</strong></p> <ul> <li>Minimum trace width</li> <li>Minimum clearance</li> <li>Minimum via size</li> <li>Maximum via count</li> <li>Length matching tolerances</li> </ul> <h2>Routing Order Strategy</h2> <p><strong>Recommended Sequence:</strong></p> <ol> <li>Power and ground planes</li> <li>High-current power traces</li> <li>Controlled impedance signals</li> <li>Differential pairs</li> <li>Critical timing signals</li> <li>General signal routing</li> <li>Test points and connections</li> </ol> <h2>Common Routing Mistakes</h2> <ol> <li><strong>Trace width too narrow</strong> - Causes overheating</li> <li><strong>Insufficient spacing</strong> - Creates crosstalk/arcing</li> <li><strong>90° angles</strong> - Causes impedance discontinuities</li> <li><strong>Long stubs</strong> - Creates signal reflections</li> <li><strong>Ignoring return paths</strong> - Degrades signal integrity</li> </ol> <h2>Advanced Techniques</h2> <h3>Length Matching</h3> <ul> <li>Use serpentines for adjustment</li> <li>Match within timing budgets</li> <li>Consider propagation delay</li> </ul> <h3>Layer Transitions</h3> <ul> <li>Use ground vias nearby</li> <li>Minimize discontinuities</li> <li>Maintain return path</li> </ul> <h2>Manufacturer Considerations</h2> <ul> <li>Verify minimum capabilities</li> <li>Check impedance tolerances</li> <li>Confirm via types supported</li> <li>Review annular ring requirements</li> </ul> <hr> <p><em>References: <a href="https://www.pcbrunner.com/a-complete-guide-to-pcb-routing-design-rules-and-best-practices-for-success/">Complete PCB Routing Guide</a>, <a href="https://www.allpcb.com/blog/pcb-design/drc-design-rule-check.html">DRC Guidelines</a>, <a href="https://resources.pcb.cadence.com/blog/2024-signal-integrity-basic">Signal Integrity Basics</a></em></p>