<h1>HDI Via Design: Comprehensive Guide</h1> <h2>Overview</h2> <p>Vias are critical interconnects in HDI PCBs, connecting layers and enabling high-density routing. This guide covers via design, types, dimensions, and best practices for HDI applications.</p> <h2>Via Types in HDI</h2> <h3>Through-Hole Vias (Traditional)</h3> <h4>Characteristics</h4> <ul> <li><strong>Diameter</strong>: 0.3mm - 0.6mm typical</li> <li><strong>Aspect Ratio</strong>: ≤10:1</li> <li><strong>Connection</strong>: Through entire board</li> <li><strong>Limitation</strong>: Consumes routing space</li> </ul> <h3>Blind Microvias</h3> <h4>Definition</h4> <p>Connect an outer layer to one or more inner layers without going through the entire board.</p> <h4>Characteristics</h4> <ul> <li><strong>Diameter</strong>: 0.075mm - 0.15mm (3-6 mil)</li> <li><strong>Depth</strong>: One or more layers</li> <li><strong>Aspect Ratio</strong>: ≤1:1 recommended</li> <li><strong>Process</strong>: Laser-drilled or mechanically drilled</li> </ul> <h4>Benefits</h4> <ul> <li>Space savings</li> <li>Improved signal integrity (shorter path)</li> <li>Better for high-frequency signals</li> <li>Reduced stub effects</li> </ul> <h3>Buried Vias</h3> <h4>Definition</h4> <p>Connect inner layers without extending to outer layers.</p> <h4>Characteristics</h4> <ul> <li><strong>Diameter</strong>: 0.15mm - 0.25mm</li> <li><strong>Depth</strong>: Between inner layers</li> <li><strong>Process</strong>: Created during lamination</li> <li><strong>Visibility</strong>: Not visible from outer layers</li> </ul> <h3>Stacked Microvias</h3> <h4>Definition</h4> <p>Multiple microvias aligned vertically, connecting multiple layers.</p> <h4>Design Rules</h4> <ol> <li><strong>Alignment</strong>: Precise registration required</li> <li><strong>Fill</strong>: Typically filled with conductive or non-conductive material</li> <li><strong>Plating</strong>: Continuous plating through stack</li> <li><strong>Reliability</strong>: Lower than staggered vias</li> </ol> <h3>Staggered Microvias</h3> <h4>Definition</h4> <p>Offset microvias in adjacent layers, connected through traces.</p> <h4>Benefits</h4> <ul> <li><strong>Reliability</strong>: Better than stacked</li> <li><strong>Manufacturing</strong>: Easier than stacked</li> <li><strong>Cost</strong>: Similar to stacked</li> </ul> <h2>Via Dimensions and Specifications</h2> <h3>Standard HDI Via Sizes</h3> <table> <thead> <tr> <th>Via Type</th> <th>Drill Size</th> <th>Finished Hole</th> <th>Pad Diameter</th> <th>Land</th> <th>Aspect Ratio</th> </tr> </thead> <tbody><tr> <td>Laser Microvia</td> <td>0.075mm</td> <td>0.10mm</td> <td>0.20mm</td> <td>0.25mm</td> <td>≤1:1</td> </tr> <tr> <td>Small Microvia</td> <td>0.10mm</td> <td>0.125mm</td> <td>0.25mm</td> <td>0.30mm</td> <td>≤0.8:1</td> </tr> <tr> <td>Standard Microvia</td> <td>0.15mm</td> <td>0.18mm</td> <td>0.30mm</td> <td>0.35mm</td> <td>≤0.8:1</td> </tr> </tbody></table> <h2>Via-in-Pad Design</h2> <h3>Benefits</h3> <h4>Electrical</h4> <ul> <li><strong>Reduced Inductance</strong>: Shorter path</li> <li><strong>Improved Signal Integrity</strong>: Minimized stubs</li> <li><strong>Better High-Frequency Performance</strong>: Less impedance discontinuity</li> </ul> <h4>Mechanical</h4> <ul> <li><strong>Space Savings</strong>: No escape routing needed</li> <li><strong>Smaller Footprint</strong>: Enables tighter component placement</li> <li><strong>Better for Fine Pitch</strong>: Essential for &lt;0.5mm pitch BGAs</li> </ul> <h3>Design Process</h3> <h4>1. Via Drilling</h4> <ul> <li>Use laser drilling for small vias</li> <li>Ensure proper location accuracy</li> <li>Maintain minimum distance from pad edge</li> </ul> <h4>2. Plating</h4> <ul> <li>Standard copper plating (25μm minimum)</li> <li>Ensure good coverage</li> <li>Verify plating quality</li> </ul> <h4>3. Fill Materials</h4> <p><strong>Conductive Epoxy Fill</strong></p> <ul> <li>Silver-filled epoxy</li> <li>Improves thermal conductivity</li> <li>Provides electrical path</li> <li>Used for thermal or ground vias</li> </ul> <p><strong>Non-Conductive Epoxy Fill</strong></p> <ul> <li>Dielectric material</li> <li>Provides planar surface</li> <li>Does not conduct electricity</li> <li>Used for signal vias</li> </ul> <h2>Via Current Capacity</h2> <h3>Approximation Formula</h3> <p>For external vias with 10°C rise: I = 0.8 × d^1.3</p> <p>Where:</p> <ul> <li>I = Current in amps</li> <li>d = Via diameter in mils</li> </ul> <h3>Via Current Capacity Table</h3> <table> <thead> <tr> <th>Finished Hole Size</th> <th>10°C Rise</th> <th>20°C Rise</th> <th>30°C Rise</th> </tr> </thead> <tbody><tr> <td>0.15mm (6 mil)</td> <td>0.7A</td> <td>1.0A</td> <td>1.3A</td> </tr> <tr> <td>0.20mm (8 mil)</td> <td>1.0A</td> <td>1.4A</td> <td>1.8A</td> </tr> <tr> <td>0.25mm (10 mil)</td> <td>1.4A</td> <td>1.9A</td> <td>2.4A</td> </tr> <tr> <td>0.30mm (12 mil)</td> <td>1.7A</td> <td>2.4A</td> <td>3.0A</td> </tr> </tbody></table> <h3>Multiple Vias for High Current</h3> <ul> <li>Use multiple vias in parallel</li> <li>Space evenly for current sharing</li> <li>Consider thermal relief</li> </ul> <h2>Common Via Design Mistakes</h2> <table> <thead> <tr> <th>Mistake</th> <th>Impact</th> <th>Solution</th> </tr> </thead> <tbody><tr> <td>Insufficient annular ring</td> <td>Breakout, poor reliability</td> <td>Follow IPC minimums</td> </tr> <tr> <td>Poor aspect ratio</td> <td>Plating voids, opens</td> <td>Keep ≤1:1 for microvias</td> </tr> <tr> <td>Inadequate clearance</td> <td>Shorts, spacing violations</td> <td>Check design rules</td> </tr> <tr> <td>Via stubs in high-speed</td> <td>Signal reflections</td> <td>Use microvias or back-drill</td> </tr> <tr> <td>No thermal relief</td> <td>Soldering issues</td> <td>Use thermal relief for plane connections</td> </tr> </tbody></table> <hr> <p><strong>References</strong>: IPC-2226, IPC-6016, IPC-6012, IPC-2152</p>