<h1>Impedance Routing 2025: Complete Guide to Controlled Impedance Design</h1> <h2>Overview</h2> <p>Controlled impedance routing is essential for high-speed digital circuits, RF applications, and any design where signal integrity is critical. This guide covers impedance calculation, routing techniques, and best practices for 2025.</p> <h2>What is Impedance?</h2> <h3>Definition</h3> <p>Impedance (Z) is the total opposition to current flow in an AC circuit, combining resistance (R) and reactance (X).</p> <h3>Characteristic Impedance</h3> <p>The characteristic impedance (Z₀) of a transmission line is the ratio of voltage to current for a wave propagating along the line.</p> <h3>Why Control Impedance?</h3> <h4>Signal Integrity</h4> <ul> <li>Prevents signal reflections</li> <li>Minimizes overshoot and undershoot</li> <li>Reduces ringing and oscillations</li> <li>Maintains signal fidelity</li> </ul> <h4>Power Transfer</h4> <ul> <li>Maximum power transfer occurs when impedances match</li> <li>Minimizes signal loss</li> <li>Optimizes performance</li> </ul> <h2>Types of Controlled Impedance</h2> <h3>Single-Ended Impedance</h3> <h4>Applications</h4> <ul> <li>General signal routing</li> <li>Clock signals</li> <li>Address/data buses</li> <li>Most digital signals</li> </ul> <h4>Common Values</h4> <ul> <li><strong>50Ω</strong>: Most common for RF and high-speed digital</li> <li><strong>75Ω</strong>: Video and RF applications</li> <li><strong>Other</strong>: Application-specific</li> </ul> <h3>Differential Impedance</h3> <h4>Applications</h4> <ul> <li>USB (Universal Serial Bus)</li> <li>PCIe (PCI Express)</li> <li>Ethernet (RJ45)</li> <li>SATA</li> <li>HDMI</li> <li>DDR memory</li> </ul> <h4>Common Values</h4> <ul> <li><strong>90Ω</strong>: USB 2.0/3.x</li> <li><strong>85Ω</strong>: PCIe</li> <li><strong>100Ω</strong>: Ethernet</li> <li><strong>100Ω</strong>: SATA</li> <li><strong>Other</strong>: Application-specific</li> </ul> <h3>Differential vs. Single-Ended</h3> <table> <thead> <tr> <th>Aspect</th> <th>Differential</th> <th>Single-Ended</th> </tr> </thead> <tbody><tr> <td>Noise Immunity</td> <td>Excellent</td> <td>Moderate</td> </tr> <tr> <td>EMI</td> <td>Lower</td> <td>Higher</td> </tr> <tr> <td>Cost</td> <td>Higher</td> <td>Lower</td> </tr> <tr> <td>Complexity</td> <td>Higher</td> <td>Lower</td> </tr> <tr> <td>Power</td> <td>Two signals</td> <td>One signal</td> </tr> </tbody></table> <h2>Transmission Line Types</h2> <h3>Microstrip</h3> <h4>Definition</h4> <p>A trace on the outer layer with a reference plane beneath.</p> <h4>Structure</h4> <pre><code>Dielectric -------------- Reference Plane (Ground or Power) </code></pre> <h4>Impedance Formula</h4> <p>Z₀ = (87 / sqrt(εr + 1.41)) × ln(5.98h / (0.8w + t))</p> <p>Where:</p> <ul> <li>Z₀ = Characteristic impedance (Ω)</li> <li>εr = Dielectric constant of material</li> <li>h = Height of dielectric</li> <li>w = Trace width</li> <li>t = Trace thickness</li> </ul> <h4>Pros</h4> <ul> <li>Easier to fabricate</li> <li>Lower impedance</li> <li>Better for moderate frequencies</li> <li>Easy to access for probing</li> </ul> <h4>Cons</h4> <ul> <li>More EMI radiation</li> <li>Susceptible to external noise</li> <li>Not suitable for very high frequencies</li> </ul> <h3>Stripline</h3> <h4>Definition</h4> <p>A trace sandwiched between two reference planes.</p> <h4>Structure</h4> <pre><code>-------------- Reference Plane Dielectric Trace Dielectric Reference Plane -------------- </code></pre> <h4>Impedance Formula</h4> <p>Z₀ = (60 / sqrt(εr)) × ln(4h / (0.67π(w + t)(0.8 + t/h)))</p> <p>Where:</p> <ul> <li>Z₀ = Characteristic impedance (Ω)</li> <li>εr = Dielectric constant</li> <li>h = Distance between planes</li> <li>w = Trace width</li> <li>t = Trace thickness</li> </ul> <h4>Pros</h4> <ul> <li>Lower EMI</li> <li>Better noise immunity</li> <li>Suitable for very high frequencies</li> <li>Controlled impedance</li> </ul> <h4>Cons</h4> <ul> <li>Harder to fabricate</li> <li>Higher impedance typically</li> <li>Not accessible for probing</li> <li>More expensive</li> </ul> <h3>Coplanar Waveguide</h3> <h4>Definition</h4> <p>Signal trace with ground traces on same layer on both sides.</p> <h4>Structure</h4> <pre><code>Ground Trace Signal Trace Ground Trace ---------------------------------------- Dielectric Reference Plane </code></pre> <h4>Applications</h4> <ul> <li>RF circuits</li> <li>Microwave applications</li> <li>High-frequency designs</li> <li>Where precise impedance control needed</li> </ul> <h2>Impedance Calculation</h2> <h3>Material Properties</h3> <h4>Dielectric Constant (Dk or εr)</h4> <p>The ability of a material to store electrical energy in an electric field.</p> <table> <thead> <tr> <th>Material</th> <th>Dk (Typical)</th> <th>Application</th> </tr> </thead> <tbody><tr> <td>FR-4 Standard</td> <td>4.3-4.8</td> <td>General purpose</td> </tr> <tr> <td>FR-4 High-Speed</td> <td>3.8-4.2</td> <td>High-speed digital</td> </tr> <tr> <td>Rogers RO4003C</td> <td>3.38</td> <td>RF/microwave</td> </tr> <tr> <td>Rogers RO4350B</td> <td>3.48</td> <td>RF/microwave</td> </tr> <tr> <td>Isola FR408HR</td> <td>3.7-3.9</td> <td>High-speed</td> </tr> </tbody></table> <h4>Dissipation Factor (Df or tan δ)</h4> <p>Measure of signal loss in the material.</p> <table> <thead> <tr> <th>Material</th> <th>Df (Typical)</th> <th>Loss</th> </tr> </thead> <tbody><tr> <td>FR-4 Standard</td> <td>0.020</td> <td>High loss at high frequency</td> </tr> <tr> <td>FR-4 High-Speed</td> <td>0.010-0.015</td> <td>Moderate loss</td> </tr> <tr> <td>Rogers RO4003C</td> <td>0.0027</td> <td>Low loss</td> </tr> <tr> <td>Rogers RO4350B</td> <td>0.0037</td> <td>Low loss</td> </tr> </tbody></table> <h3>Calculation Tools</h3> <h4>Online Calculators</h4> <ul> <li>Saturn PCB Design Toolkit</li> <li>EEWeb Impedance Calculator</li> <li>PCB Impedance Calculator</li> <li>Manufacturer-specific tools</li> </ul> <h4>PCB Design Software</h4> <ul> <li>Altium Designer: Built-in impedance calculator</li> <li>Cadence Allegro: SI tools</li> <li>Mentor Graphics: HyperLynx</li> <li>KiCad: Built-in calculator</li> <li>Most tools: Integrated calculators</li> </ul> <h2>Design Guidelines</h2> <h3>Microstrip Design Rules</h3> <h4>Target 50Ω Single-Ended</h4> <p>For FR-4 (εr = 4.5) with 1 oz copper (t = 0.035mm):</p> <table> <thead> <tr> <th>Dielectric Thickness (h)</th> <th>Trace Width (w)</th> </tr> </thead> <tbody><tr> <td>0.1mm</td> <td>0.18mm</td> </tr> <tr> <td>0.2mm</td> <td>0.38mm</td> </tr> <tr> <td>0.3mm</td> <td>0.58mm</td> </tr> <tr> <td>0.4mm</td> <td>0.79mm</td> </tr> <tr> <td>0.5mm</td> <td>1.0mm</td> </tr> </tbody></table> <h4>Target 90Ω Differential</h4> <p>For FR-4 (εr = 4.5) with 1 oz copper (t = 0.035mm) and 0.2mm dielectric:</p> <table> <thead> <tr> <th>Trace Width</th> <th>Trace Spacing</th> <th>Differential Impedance</th> </tr> </thead> <tbody><tr> <td>0.15mm</td> <td>0.15mm</td> <td>~90Ω</td> </tr> <tr> <td>0.20mm</td> <td>0.20mm</td> <td>~85Ω</td> </tr> <tr> <td>0.10mm</td> <td>0.10mm</td> <td>~95Ω</td> </tr> </tbody></table> <h3>Stripline Design Rules</h3> <h4>Target 50Ω Single-Ended</h4> <p>For FR-4 (εr = 4.5) centered between planes (h = total spacing/2):</p> <table> <thead> <tr> <th>Plane-to-Plane Spacing</th> <th>Trace Width (w)</th> </tr> </thead> <tbody><tr> <td>0.2mm</td> <td>0.15mm</td> </tr> <tr> <td>0.3mm</td> <td>0.23mm</td> </tr> <tr> <td>0.4mm</td> <td>0.31mm</td> </tr> <tr> <td>0.5mm</td> <td>0.39mm</td> </tr> </tbody></table> <h2>Routing Best Practices</h2> <h3>General Routing</h3> <h4>1. Maintain Constant Impedance</h4> <ul> <li>Keep trace width constant</li> <li>Maintain constant distance to reference plane</li> <li>Avoid changing layers (if possible)</li> <li>If changing layers, use impedance-matched vias</li> </ul> <h4>2. Reference Planes</h4> <ul> <li>Provide continuous reference plane</li> <li>Avoid splits in reference plane under traces</li> <li>Use stitching vias near layer transitions</li> <li>Maintain plane integrity</li> </ul> <h4>3. Avoid Discontinuities</h4> <ul> <li>Smooth corners (45° or curved)</li> <li>No 90° corners</li> <li>Proper via selection</li> <li>Minimize layer changes</li> </ul> <h3>Differential Pair Routing</h3> <h4>1. Length Matching</h4> <ul> <li>Match lengths within tolerance</li> <li>Typical tolerance: 5-10 mils</li> <li>Use serpentine routing for matching</li> <li>Match within pair, not to other pairs</li> </ul> <h4>2. Spacing</h4> <ul> <li>Maintain constant spacing</li> <li>Keep spacing consistent</li> <li>Avoid obstacles in pair</li> <li>Minimize layer changes</li> </ul> <h4>3. Symmetry</h4> <ul> <li>Route symmetrically</li> <li>Keep equal distances to obstacles</li> <li>Use same via patterns</li> <li>Maintain symmetry throughout</li> </ul> <h4>4. Layer Changes</h4> <ul> <li>Change both signals simultaneously</li> <li>Use paired vias</li> <li>Maintain spacing through vias</li> <li>Consider impedance discontinuities</li> </ul> <h2>Impedance Testing</h2> <h3>Time Domain Reflectometry (TDR)</h3> <h4>How It Works</h4> <ul> <li>Sends fast edge down transmission line</li> <li>Measures reflections</li> <li>Displays impedance vs. distance</li> <li>Identifies impedance discontinuities</li> </ul> <h4>TDR Specifications</h4> <ul> <li><strong>Rise Time</strong>: &lt; 35ps for high-impedance accuracy</li> <li><strong>Resolution</strong>: &lt; 1mm typical</li> <li><strong>Accuracy</strong>: ±5-10% typical</li> </ul> <h3>Test Coupons</h3> <h4>Purpose</h4> <ul> <li>Verify impedance during fabrication</li> <li>Test representative traces</li> <li>Calibrate process</li> <li>Ensure quality control</li> </ul> <h4>Design</h4> <ul> <li>Include on panel</li> <li>Use same layer stack</li> <li>Representative trace geometries</li> <li>Include various impedances</li> </ul> <h2>Common Impedance Issues</h2> <table> <thead> <tr> <th>Issue</th> <th>Cause</th> <th>Solution</th> </tr> </thead> <tbody><tr> <td>Reflections</td> <td>Impedance mismatch</td> <td>Match impedances properly</td> </tr> <tr> <td>Ringing</td> <td>Improper termination</td> <td>Add proper termination</td> </tr> <tr> <td>EMI</td> <td>Poor return path</td> <td>Provide solid reference plane</td> </tr> <tr> <td>Crosstalk</td> <td>Traces too close</td> <td>Increase spacing</td> </tr> <tr> <td>Loss</td> <td>Wrong material or trace</td> <td>Use lower-loss material</td> </tr> </tbody></table> <h2>Advanced Topics</h2> <h3>Via Stubs</h3> <h4>Problem</h4> <ul> <li>Via acts as transmission line stub</li> <li>Causes reflections at high frequencies</li> <li>Degrades signal integrity</li> </ul> <h4>Solutions</h4> <ul> <li><strong>Back-drilling</strong>: Remove unused portion of via</li> <li><strong>Microvias</strong>: Smaller, shorter vias</li> <li><strong>Via-in-pad</strong>: Eliminates stub completely</li> </ul> <h3>High-Speed Considerations</h3> <h4>Frequency-Dependent Losses</h4> <ul> <li><strong>Dielectric Loss</strong>: Material property</li> <li><strong>Copper Loss</strong>: Skin effect, surface roughness</li> <li><strong>Radiation Loss</strong>: Improper termination or routing</li> </ul> <h4>Skin Effect</h4> <ul> <li>Current flows on conductor surface at high frequencies</li> <li>Increases effective resistance</li> <li>More significant above 1 GHz</li> <li>Consider copper surface roughness</li> </ul> <hr> <p><strong>References</strong>: IPC-2141, IPC-2251, IPC-2221</p>